Job Description
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- Performs functional logic verification of an IP and/or subsystem to ensure design will meet specification requirements.
- Develops FPGA IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the FPGA design and uncover bugs.
- Replicates, root causes, and debugs issues in the pre-silicon environment.
- Finds and implements corrective measures to resolve failing tests.
- Collaborates with FPGA architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. May also collaborate with systems and software engineers to support integration testing of the FPGA.
- Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.
- Maintains and improves existing functional verification infrastructure and methodology.
- Documents, reviews, and executes the verification strategy plan on different methodologies/techniques (e.g., gate-level-simulation strategy, power patterns/aware simulations) used to enable feature coverage as per the microarchitecture specifications.
Job Details Job Description: - Performs functional logic verification of an IP and/or subsystem to ensure design will meet specification requirements.
- Develops FPGA IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the FPGA design and uncover bugs.
- Replicates, root causes, and debugs issues in the pre-silicon environment.
- Finds and implements corrective measures to resolve failing tests.
- Collaborates with FPGA architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. May also collaborate with systems and software engineers to support integration testing of the FPGA.
- Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.
- Maintains and improves existing functional verification infrastructure and methodology.
- Documents, reviews, and executes the verification strategy plan on different methodologies/techniques (e.g., gate-level-simulation strategy, power patterns/aware simulations) used to enable feature coverage as per the microarchitecture specifications.
Salary Range The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$210k - $280k USD
Qualifications - BS in Electrical Engineering, Computer Science or related field.
- 8+ years of experience in design verification in IP or subsystem
- Demonstrated knowledge of System Verilog and UVM. Formal and emulation is a plus.
- Proven ability to have done the full verification lifecycle from testplans, environment ownership, coverage closure and bug tracking etc.
Job Type Regular
Shift Shift 1 (United States of America)
Primary Location: San Jose, California, United States
Additional Locations: Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Seniority level
Seniority level
Mid-Senior level
Employment type
Employment type
Full-time
Job function
Job function
Engineering and Information Technology Industries
Semiconductor Manufacturing
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Job Tags
Full time, Local area, Shift work,